Capacitor-embedded substrate and method of manufacturing the same

ABSTRACT

A capacitor-embedded substrate includes a base material having a desired thickness, and a pair of conductors (feedthrough electrodes) each formed in a desired pattern to penetrate through the base material in the thickness direction thereof, and oppositely disposed with an insulating layer interposed therebetween. The pair of electrodes are formed in comb-shaped patterns, and are oppositely disposed in such a manner that respective comb-tooth portions are meshed with each other.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on and claims priority of Japanese PatentApplication No. 2007-236663 filed on Sep. 12, 2007, the entire contentsof which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a substrate having a capacitor embeddedtherein and, more particularly, to a capacitor-embedded substrate to beused as a base material for a multilayer wiring board or a module, or asan interposer, in each of which a semiconductor device (or chip), anelectronic component or the like requiring high speed switchingoperation is mounted, and a method of manufacturing the same.

As employed herein, the multilayer wiring board is also referred to as a“semiconductor package” for the sake of convenience in the descriptionbelow, in consideration of the function as a package for mountingsemiconductor devices (or chips) or the like.

(b) Description of the Related Art

Semiconductor packages or the like have been recently required to havefiner and denser wiring, and thus have been provided with wiringpatterns in close proximity to each other. Such wiring patterns,however, can possibly cause a problem such as occurrence of crosstalknoise between wirings or variations in the potential of a power supplyline or the like. In particular, in a package for mounting asemiconductor chip, an electronic component or the like required toperform high speed switching operation, the crosstalk noise is easy tobe generated due to the rise in frequency, and also, high speed on-offoperation of a switching element produces switching noise, so thatvariations in the potential of the power supply line or the like areeasy to increase. To cope with this, packages for mounting semiconductorchips or the like have hitherto been provided with a chip capacitor for“decoupling” power supply lines or the like for the purposes ofstabilization of power supply voltage and reduction in switching noisesor the like.

However, this situation can possibly lead to the design freedom of thewiring pattern being restricted in accordance with the provision of thechip capacitor, or may possibly increase the routing length of thewiring pattern that connects the chip capacitor to a power supply/groundterminal of the semiconductor chip or the like, resulting in an increasein inductance. The smallest possible inductance is desirable becauselarge inductance degreases a decoupling effect.

Instead of providing a chip capacitor to a package, other possible meansfor coping with the above problem is to provide an equivalentcapacitative device inside a package. Also, the technologies ofembedding a capacitor function into a substrate for passive componentshave come into practical use, accompanied by recent miniaturization andslimming-down of electronic devices such as mobile devices or portabledevices. One of the technologies is to form a buried electrode in aninsulating layer of the substrate by using a high-permittivityinsulating sheet. In a typical configuration example of this technology,a high-permittivity insulating resin sheet (e.g., resin sheet containingan inorganic filler for enhancement of permittivity) is disposed as adielectric of the capacitor in an organic resin substrate, and conductorlayers (i.e., wiring layers) that form a pair of electrodes of thecapacitor are provided on the resin sheet with being interposedtherebetween.

One example of a technology related to the above conventional technologyis disclosed in Japanese unexamined Patent Publication (Kokai)2007-150180. The technology disclosed in this publication involves:providing at least one surface of a base material having flexibilitywith a wiring pattern; forming a circuit component monolithicallyintegrated with the base material by filling a predetermined materialinto a groove formed in the one surface with a predetermined depth andin a predetermined pattern shape; and providing a connection between thecircuit component and the wiring pattern, thereby forming a flexiblecircuit board. This flexible circuit board includes as one circuitcomponent a capacitor constituted by: a pair of comb-shaped electrodesformed by filling an electrode material into grooves that are formedinto comb-shaped patterns facing each other; and a dielectric layerformed by base material between the pair of comb-shaped electrodes.

As mentioned above, the technology of embedding the capacitor functioninto the semiconductor package has been brought into practical useaccompanied by the recent miniaturization or the like of the electronicdevice and for the purposes of effective functioning of the decouplingeffect. In this case, it is desirable that the capacitor have thelargest possible capacitance in order to optimize the function as acapacitor. However, an attempt to increase the capacitance of thecapacitor involves various problems as given below.

Specifically, a high-permittivity insulating resin sheet (with apermittivity about 45) as mentioned above has a considerably low valueof the permittivity, compared with a conventionally-used ceramic chipcapacitor (with a permittivity of about 20000). Therefore, consideringthe formation of the capacitor having larger capacitance (around 100nF), achievement for the desired capacitance requires: an increase insize of the facing area of the electrodes having the sheet sandwichedtherebetween; a reduction in thickness of the sheet (i.e., the distancebetween the electrodes); or a further heightening of the permittivity.To heighten the permittivity requires an increase in a content rate ofthe inorganic filler in the high-permittivity insulating resin sheet;however, there are technological limitations under the presentcircumstances. Meanwhile, as for the approach of reducing the thicknessof the high-permittivity insulating resin sheet, the technology itselfhas its limitations for forming a thin resin sheet. Even if the sheet issuccessfully thinly formed in a desired thickness, the thinly formedsheet is fully expected to become difficult to handle.

On the other hand, the increase in size of the facing area of theelectrodes (i.e., a portion of the conductor layer) having thehigh-permittivity insulating resin sheet sandwiched therebetweenrequires allocation of almost all portions of the conductor layerssolely to the electrodes, which in turn increases the area occupied bythe electrodes in the conductor layers and thus accordingly impairs thedegree of freedom of other wirings. Another approach for the increase insize of the facing area of the electrodes is to alternately stack on topof each other the insulating layers (i.e., resin layers) that form thedielectrics, and the conductor layers that form the electrodes; however,it is required that the layers be formed one by one, as in the case ofbuild-up process, which in turn increases the process time and henceleads to a rise in cost. Additionally, still another possible approachfor the increase in size of the facing area of the electrodes is to forma staggered arrangement of the dielectrics (i.e., the insulating layers)and the electrodes (i.e., the conductor layers) to form a comb-shapedstructure (namely, a parallel capacitor); however, with this approach,it is difficult to form a multilayer structure.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a capacitor-embeddedsubstrate and a method of manufacturing the same, capable offacilitating implementation of a capacitor function adapted to largercapacitance.

Another object of the present invention is to provide a method ofmanufacturing a capacitor-embedded substrate, capable of contributing toa reduction in manufacturing cost and an improvement in the degree ofwiring freedom.

According to one aspect of the present invention, there is provided acapacitor-embedded substrate including: a base material having a desiredthickness; and a pair of conductors formed in respective desiredpatterns to penetrate through the base material in a thickness directionthereof, and oppositely disposed with an insulating layer interposedtherebetween.

With the configuration of the capacitor-embedded substrate according tothis aspect, a pair of the conductors formed penetrating through thebase material having the desired thickness in the thickness directionthereof are utilized as feedthrough electrodes of the capacitor, and theinsulating layer interposed between the conductors is utilized as adielectric layer of the capacitor. In other words, the capacitor isformed in three dimension within the base material, so that thecapacitor is adaptable to larger capacitance. For example, the pair ofthe conductors are formed in a shape of a comb-shaped pattern and areoppositely disposed in such a manner that respective comb-tooth portionsare meshed with each other, thereby enabling an increase in the facingarea between the electrodes and hence a contribution to achievement oflarger capacitance, even if the capacitor is formed into a small area.

Also, according to another aspect of the present invention, there isprovided a method of manufacturing a capacitor-embedded substrate,including: forming an opening in a desired pattern penetrating through abase material having a desired thickness in a thickness directionthereof; forming an insulating layer on an inner wall surface of theopening; filling a conductor into the opening coated with the insulatinglayer; removing a portion of the base material interposed between theinsulating layers; and filling the removed portion with a conductor.

Detailed description is given with reference to embodiments of thepresent invention with regard to other structural features andadvantages and the like based thereon, of the capacitor-embeddedsubstrate and the method of manufacturing the same according to thepresent invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are views showing the configuration of acapacitor-embedded substrate according to a first embodiment of thepresent invention, and FIG. 1A is a plan view thereof and FIG. 1B is asectional view taken along the line A-A′ of FIG. 1A;

FIGS. 2A to 2D are sectional views showing manufacturing steps for thecapacitor-embedded substrate shown in FIGS. 1A and 1B;

FIGS. 3A to 3D are sectional views showing manufacturing steps followingthe steps shown in FIGS. 2A to 2D;

FIGS. 4A to 4D are sectional views showing manufacturing steps followingthe steps shown in FIGS. 3A to 3D;

FIGS. 5A, 5B and 5C are views showing the configuration of acapacitor-embedded substrate according to a second embodiment of thepresent invention, and FIG. 5A is a plan view thereof, FIG. 5B is anenlarged plan view at “P” portion shown in FIG. 5A, and FIG. 5C is asectional view taken along the line B-B′ of FIG. 5B;

FIGS. 6A and 6B are views showing the configuration of acapacitor-embedded substrate according to a third embodiment of thepresent invention, and FIG. 6A is a plan view thereof and FIG. 6B is asectional view taken along the line C-C′ of FIG. 6A;

FIGS. 7A to 7C are sectional views showing manufacturing steps for thecapacitor-embedded substrate shown in FIGS. 6A and 6B;

FIGS. 8A and 8B are sectional views showing manufacturing stepsfollowing the steps shown in FIGS. 7A to 7C; and

FIG. 9 is a sectional view schematically showing an example of theconfiguration of a module using any one of the capacitor-embeddedsubstrates according to the embodiments of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Description is given below with regard to preferred embodiments of thepresent invention with reference to the accompanying drawings.

First Embodiment See FIGS. 1A to 4D

FIGS. 1A and 1B schematically show the configuration of acapacitor-embedded substrate according to the first embodiment of thepresent invention. FIG. 1A illustrates a plan configuration thereof andFIG. 1B illustrates a sectional configuration thereof when viewed alongthe line A-A′ of FIG. 1A.

As shown in FIGS. 1A and 1B, a capacitor-embedded substrate 10 accordingto the first embodiment is basically constituted by: a silicon (Si)substrate 11 used as a base material; an insulating layer 14 made ofsilicon dioxide (SiO₂), and formed on the inner wall surfaces of twoopenings each formed in a comb-shaped pattern penetrating through the Sisubstrate 11 in the thickness direction thereof; and conductors 12 and13 made of copper (Cu), filled into each opening coated with theinsulating layer 14. The conductors 12 and 13 constitute electrodes ofthe capacitor, and the insulating layer 14 constitutes a dielectriclayer of the capacitor. The electrodes 12 and 13 are oppositely disposedin such a manner that respective comb-tooth portions of the comb-shapedpattern are meshed with each other. Also, the insulating layer 14 isformed on the inner wall surfaces of the openings, while the insulatinglayer 14 is formed in such a manner as to be shared between theelectrodes 12 and 13 in a location where the comb-tooth portions of theelectrodes 12 and 13 are oppositely formed, as shown in FIGS. 1A and 1B.

The first embodiment is characterized in that the conductors 12 and 13formed penetrating through the Si substrate 11 in the thicknessdirection thereof are configured as the electrodes (namely, feedthroughelectrodes) of the capacitor and the insulating layer (SiO₂) 14interposed between the electrodes 12 and 13 is configured as thedielectric layer of the capacitor, or equivalently, in that thecapacitor is formed in three dimension within the Si substrate 11. Inthis instance, the insulating layer 14 that forms the dielectric layerof the capacitor is made of SiO₂ and thus has relatively lowpermittivity. Therefore, a “comb-shaped” electrode structure as shown inFIG. 1A is adopted in order to effectively increase the capacitance ofthe capacitor. Adoption of such an electrode structure enablesincreasing the facing area of the electrodes 12 and 13 and thuscontributes to achievement of larger capacitance, even if the capacitoris formed into a small area. Incidentally, the thickness of the Sisubstrate 11 is set approximately equal to 200 μm; the thickness of eachof the electrodes 12 and 13 is set approximately equal to 60 μm; and thethickness of the dielectric layer (SiO₂) 14 is set approximately equalto 1.5 μm.

Description is given below with regard to a method of manufacturing thecapacitor-embedded substrate 10 according to the first embodiment withreference to FIGS. 2A to 4D showing an example of a manufacturingprocess thereof.

First, at the first step (see FIG. 2A), the silicon (Si) substrate 11thinly formed in a predetermined thickness is prepared. For example,this involves preparing a Si wafer of 12 inches in size and of about 725μm thick, and grinding one or both surfaces of the wafer by use of agrinding device, thereby thinning the wafer to a thickness of about 200μm.

At the next step (see FIG. 2B), an opening OP1 is formed penetratingthrough the Si substrate 11 in a desired position in a desired patternshape in the thickness direction of the Si substrate 11 by dry etchingmethod such as reactive ion etching (RIE) or sputter etching. Althoughthe openings OP1 seems as if separately formed dispersedly in ten placesas shown in the example in FIG. 2B, one opening OP1 is actually formed.This opening OP1 is filled with the conductor that forms one of theelectrodes of the capacitor, as is described later. In other words, theopening OP1 is formed in the “comb-shaped” pattern when viewed in plan(see FIG. 1A).

At the next step (see FIG. 2C), the insulating layer 14 is formed as thedielectric layer of the capacitor on the inner wall surface of theopening OP1. First, the insulating layer 14 made of silicon oxide (SiO₂)is formed throughout the entire surface of the Si substrate 11,including the inner wall of the opening OP1, by thermal oxidationmethod, CVD (chemical vapor deposition) method, vapor deposition, or thelike. Then, the Si substrate 11 having the insulating layer 14 formedthroughout the entire surface is polished at both surfaces by chemicalpolishing or chemical mechanical polishing (CMP), and continues beingpolished to become flattened, until the Si substrate 11 is exposed atboth surfaces (namely, until reaching a level where the insulating layer14 remains only on the inner wall surface of the opening OP1), as shownin FIG. 2C.

At the next step (see FIG. 2D), copper (Cu) foil 15 is applied to onesurface (the bottom side in the example in FIG. 2D) of the Si substrate11 having the insulating layer 14 formed on the inner wall surface ofthe opening OP1. The copper foil 15 functions as a seed layer (i.e., apower feed layer) for electroplating process to be performed later.

At the next step (see FIG. 3A), the Si substrate 11 having the seedlayer (i.e., the copper foil 15) formed at one surface and theinsulating layer 14 formed on the inner wall surface of the opening OP1(see FIG. 2D) is electroplated with Cu with the seed layer 15 acting asthe power feed layer, whereby the opening is filled with a conductor(Cu) 12 a.

At the next step (see FIG. 3B), the Si substrate 11 having the seedlayer 15 formed at one surface and the conductor 12 a formed at theother surface by being filled into the opening is polished at bothsurfaces by chemical polishing or CMP, and continues being polished tobecome flattened, until the Si substrate 11 is exposed at both surfacesas shown in FIG. 3B. Thereby, the formation of one of the electrodes ofthe capacitor, namely, the electrode 12 (see FIGS. 1A and 1B), isaccomplished.

At the next step (see FIG. 3C), in the same manner as the processesperformed at the steps of FIGS. 2B and 2D, an opening OP2 is formed byetching away “Si” in a portion of the Si substrate 11 interposed betweenthe insulating layers 14 (namely, the portion facing the comb-toothportion of the electrode 12 formed in the comb-shaped pattern shape) bymeans of dry etching method such as reactive ion etching (RIE) orsputter etching. Furthermore, copper (Cu) foil 16 is applied as a seedlayer to one surface (the bottom side in the example in FIG. 3C) of theSi substrate 11. The opening OP2 thus formed is filled with theconductor that forms the other electrode of the capacitor, as isdescribed later.

At the next step (see FIG. 3D), in the same manner as the processperformed at the step of FIG. 3A, the Si substrate 11 having the seedlayer (i.e., the copper foil 16) formed at one surface and the openingOP2 (see FIG. 3C) formed at the other surface is electroplated with Cuwith the seed layer 16 acting as a power feed layer, whereby the openingis filled with a conductor (Cu) 13 a.

At the next step (see FIG. 4A), in the same manner as the processperformed at the step of FIG. 3B, the Si substrate 11 having the seedlayer 16 (see FIG. 3D) formed at one surface and the conductor 13 aformed at the other surface by being filled into the opening is polishedat both surfaces by chemical polishing or CMP, and continues beingpolished to become flattened, until the Si substrate 11 is exposed atboth surfaces as shown in FIG. 4A. Thereby, the formation of the otherelectrode 13 of the capacitor is accomplished, so that the formation ofthe capacitor-embedded substrate 10 shown in FIGS. 1A and 1B isbasically accomplished.

At the next step (see FIG. 4B), insulating layers 17 made of siliconoxide (SiO₂), which function as protection films for the capacitor, areformed on both surfaces of the silicon (Si) substrate 11 of thecapacitor-embedded substrate 10 fabricated through the preceding steps,by thermal oxidation method, CVD method, vapor deposition, or the like.

At the next step (see FIG. 4C), via holes VH are formed in desiredpositions on one surface (the upper side in the example in FIG. 4C) inthe insulating layer 17 thus formed of the Si substrate 11, by means ofa CO₂ (carbon dioxide) laser, a YAG (yttrium aluminum garnet) laser, anexcimer laser, or the like. The positions where the via holes VH areformed are selected at least two positions in the insulating layerregion, corresponding respectively to the portions where the electrodes12 and 13 of the capacitor are formed.

At the final step (see FIG. 4D), wiring patterns 18 are formed in adesired shape by filling in each of the via holes VH. For example, thisinvolves forming a seed layer on the insulating layer 17 including theinside of the via hole VH by means of electroless copper (Cu) plating orthe like; either filling the via hole VH with Cu by means of Cuelectroplating with the seed layer acting as a power feed layer, orfilling conductive paste containing metal such as Cu into the via holeVH by means of screen printing method or the like; and then forming thewiring patterns 18 made of Cu in the desired shape by means ofsubtractive process, semi-additive process, ink-jet process, or thelike. The formed wiring patterns 18 can be utilized as electrodeterminals of the capacitor.

As described above, according to the capacitor-embedded substrate 10according to the first embodiment (see FIGS. 1A and 1B) and the methodof manufacturing the same (see FIGS. 2A to 4D), a pair of the conductors12 and 13 formed penetrating through the Si substrate 11 having adesired thickness in the thickness direction thereof are utilized as thefeedthrough electrodes of the capacitor, and the insulating layer (SiO₂)14 interposed between the electrodes 12 and 13 is utilized as thedielectric layer of the capacitor. In other words, the capacitor isformed in three dimension within the Si substrate 11, and further, theelectrodes 12 and 13 each have the “comb-shaped” electrode structure,thus enabling an effective increase in the facing area between theelectrodes 12 and 13 even if the capacitor is formed into a small area(or occupied area). This greatly contributes to achievement of largercapacitance of the capacitor.

Also, the formation of the dielectric layer (SiO₂) 14 of the capacitorcan be accomplished merely by thermally oxidizing or otherwiseprocessing the inner wall surface of the opening formed in the Sisubstrate 11 in the desired position, using the Si substrate 11 as thebase material. In other words, the formation of the dielectric layer 14of multilayer structure can be accomplished in a single step (see FIG.2C), thus enabling a simplification of process and hence a contributionto a reduction in manufacturing cost, as compared with the conventionalapproach of alternately stacking on top of each other the insulatinglayers (i.e., the dielectric layers) and the conductor layers (i.e., theelectrodes).

Also, where the capacitor-embedded substrate 10 is utilized as aninterposer, the same material, namely “Si,” as a constituent materialfor a semiconductor chip (typically, a silicon (Si) chip) mounted on theinterposer is used for the base material 11, so that the coefficient ofthermal expansion of the mounted chip can be substantially equal to thatof the base material 11. This enables elimination of a disadvantage suchas warpage or torsion resulting from a difference in heat shrinkagebetween the chip and the base material.

Second Embodiment See FIGS. 5A to 5C

FIGS. 5A, 5B and 5C schematically show the configuration of acapacitor-embedded substrate according to the second embodiment of thepresent invention. FIG. 5A illustrates a plan configuration thereof,FIG. 5B shows a plan configuration thereof when viewed in enlarged viewat “P” portion shown in FIG. 5A, and FIG. 5C shows a sectionalconfiguration thereof when viewed along the line B-B′ of FIG. 5B,respectively.

A capacitor-embedded substrate 20 according to the second embodiment isbasically constituted, as in the case of the capacitor-embeddedsubstrate 10 according to the first embodiment (see FIGS. 1A and 1B),by: a Si substrate 21 used as a base material; an insulating layer(i.e., a dielectric layer) 24 made of SiO₂, formed on the inner wallsurfaces of two openings formed in a shape of a comb-shaped patternpenetrating through the Si substrate 21 in the thickness directionthereof; and conductors (i.e., electrodes) 22 and 23 made of Cu, filledinto the openings coated with the insulating layer 24. The dispositionsof the electrodes 22 and 23 and the insulating layer 24 are the same asdescribed above for the first embodiment.

The second embodiment is further characterized in that the feedthroughelectrodes 22 and 23 to be formed within the Si substrate 21 aredividedly formed into a predetermined number of portions (namely,divided electrodes into 22 a and 22 b and divided electrodes into 23 aand 23 b, respectively); an insulating layer 25 made of SiO₂ is vapordeposited or otherwise formed on one surface (the upper side in theexample in FIGS. 5A to 5C) of the Si substrate 21; then, via holes areformed in the insulating layer 25 in desired locations; and wiringpatterns (i.e., Cu conductors) 26 and 27 are formed on the insulatinglayer 25 including the via holes, whereby the wiring patterns 26 and 27provide a connection between the two adjacent divided electrodes 22 aand 22 b and a connection between the two adjacent divided electrodes 23a and 23 b, respectively. In other words, the capacitor to beessentially formed between the electrodes 22 and 23 has a structurehaving a parallel connection of multiple small-capacitance capacitorsformed between the plural divided electrodes 22 a (22 b) and 23 a (23b). Such a structure achieves a reduction in the inductance of thecapacitor embedded in the Si substrate 21.

According to the second embodiment, further advantages can be obtainedas given below, in addition to the above-mentioned advantageous effectsobtained by the first embodiment. Specifically, it is generally knownthat the capacitor can lower its inductance when having its electrodesdivided, compared with one when having its electrodes undivided. In thesecond embodiment, the feedthrough electrodes 22 and 23 to be formedwithin the Si substrate 21 are dividedly formed into plural portions asshown in FIGS. 5A to 5C, so that the inductance (namely, ESL (equivalentseries inductance)) of the capacitor can be reduced withoutsubstantially reducing the capacitative value of the overall capacitorformed between the electrodes 22 and 23.

In addition, the inductance reduction enables boosting a resonancefrequency and thus achieving the capacitor excellent in high-frequencycharacteristics. In other words, this enables the more effectivefunctioning of the decoupling effect of the capacitor and thus acontribution to stable operation in the high-frequency region (i.e., theGHz band) for use in mobile devices, portable devices, or the like.

Third Embodiment See FIGS. 6A to 8B

FIGS. 6A and 6B schematically show the configuration of acapacitor-embedded substrate according to the third embodiment of thepresent invention. FIG. 6A illustrates a plan configuration thereof andFIG. 6B illustrates a sectional configuration thereof when viewed alongthe line C-C′ of FIG. 6A.

A capacitor-embedded substrate 30 according to the third embodiment isbasically constituted, as in the case of the capacitor-embeddedsubstrate 10 according to the first embodiment (see FIGS. 1A and 1B),by: a Si substrate 31 used acts as a base material; an insulating layer(i.e., a dielectric layer) 34 made of SiO₂, formed on the inner wallsurfaces of two openings formed in a shape of a comb-shaped patternpenetrating through the Si substrate 31 in the thickness directionthereof; and conductors (i.e., electrodes) 32 and 33 made of Cu, filledinto the openings coated with the insulating layer 34. The dispositionsof the electrodes 32 and 33 and the insulating layer 34 are the same asdescribed above for the first embodiment.

The third embodiment is further characterized in that a conductor (i.e.,a second feedthrough electrode) 36 made of Cu is formed within theelectrodes (i.e., first feedthrough electrodes) 32 and 33 of thecapacitor in such a relationship that the electrode 36 is insulated fromthe electrodes 32 and 33 (by an insulating layer 35 made of SiO₂). Inother words, a double-feedthrough-electrode construction is adopted inwhich another feedthrough electrode is formed within the feedthroughelectrodes of the capacitor. Such a construction achieves an improvementin the degree of wiring freedom of the substrate.

The capacitor-embedded substrate 30 according to the third embodimentcan be manufactured basically in the same manner as the method ofmanufacturing the capacitor-embedded substrate 10 according to the firstembodiment (see FIGS. 2A to 4D). FIGS. 7A to 7C and FIGS. 8A and 8Bschematically show a manufacturing process for the capacitor-embeddedsubstrate 30.

Specifically, the manufacture of the capacitor-embedded substrate 30according to the third embodiment is accomplished by: going through thesame process as that performed at the step of FIG. 2A; thereafterperforming “silicon (Si) etching” in the same manner as the processingperformed at the step of FIG. 2B (see FIG. 7A); then performing “theformation of the insulating layers 34 and 35 by means of thermaloxidation or the like, and the polishing of both surfaces of the Sisubstrate 31” in the same manner as the process performed at the step ofFIG. 2C (see FIG. 7B); then performing “the application of a seed layer,the filling of conductors into openings OP3 and OP4 by means of copper(Cu) electroplating, and the polishing of both surfaces of the Sisubstrate 31” in the same manner as the processes performed at the stepsof FIGS. 2D to 3B (see FIG. 7C); then performing “Si etching” in thesame manner as the process performed at the step of FIG. 3C (see FIG.8A); and then performing “the application of a seed layer, the fillingof conductors into openings OP5 and OP6 by means of copper (Cu)electroplating, and the polishing of both surfaces of the Si substrate31” in the same manner as the processes performed at the steps of FIGS.3D to 4A (see FIG. 8B).

Note, the step of FIG. 7A includes concurrently the formation of theopening OP4 such that a portion of the Si substrate 31 corresponding tothe shape of the second feedthrough electrode 36 remains, as well as theformation of the opening OP3 defining the shape of one of the electrodesof the capacitor, namely, the electrode 33. Also, the step of FIG. 7Bincludes concurrently the formation of the insulating layer 35 forinsulating the second feedthrough electrode 36 from the firstfeedthrough electrode 33, as well as the formation of the insulatinglayer 34 as the dielectric layer of the capacitor. Also, the step ofFIG. 7C includes concurrently the formation of the first feedthroughelectrode 33 to finally contain the second feedthrough electrode 36, aswell as the formation of the one electrode 33 of the capacitor.

Also, the step of FIG. 8A includes concurrently the formation of theopening OP6 in the portion of the Si substrate 31 corresponding to theshape of the second feedthrough electrode 36, as well as the formationof the opening OP5 defining the shape of the other electrode 32 of thecapacitor. Also, the step of FIG. 8B includes concurrently the formationof the second feedthrough electrode 36, as well as the formation of theother electrode 32 of the capacitor.

According to the third embodiment, further advantages can be obtained asgiven below, in addition to the above-mentioned advantageous effectsachieved by the first embodiment. Specifically, there is providedanother feedthrough electrode (i.e., the second feedthrough electrode)36 within the electrodes (i.e., the first feedthrough electrodes) 32 and33 of the capacitor in such a relationship that the electrode 36 isinsulated from the electrodes 32 and 33, so that other signal lineshaving no relation with the capacitor (e.g., a signal line linked to anexternal connection terminal) can be connected to the second feedthroughelectrode 36 as needed, thus enabling enhancement of the degree offreedom of the wirings of the substrate 30.

Preferably, the capacitor-embedded substrates 10, 20 and 30 according tothe above-mentioned embodiments can be utilized as a base material or aninterposer for a multilayer wiring board or a module both mounting asemiconductor device (or chip), an electronic component or the liketherein requiring high speed operation. In that case, thecapacitor-embedded substrates 10, 20 and 30 may be utilized separately,or two or more types of substrates may be utilized in combination asappropriate. FIG. 9 shows an example of application of thecapacitor-embedded substrate, schematically illustrating an example ofthe configuration of a module using the capacitor-embedded substrate.

The exemplary configuration of a module 40 shown as an example in FIG. 9uses the capacitor-embedded substrate 30 according to the thirdembodiment, and there are provided: a multilayer wiring structure 41formed on one surface of the substrate 30 by use of build-up process orthe like; further, plural chips 42, 43 and 44 (e.g., semiconductor chipssuch as a CPU (central processing unit) or an oscillator for an RF(radio-frequency) module) mounted on the multilayer wiring structure 41;and also, solder bumps 45 as external connection terminals on the othersurface of the substrate 30. Such a module 40 is mounted on a mountboard (not shown) such as a motherboard.

As for connections between the capacitor-embedded substrate 30 and themultilayer wiring structure 41 and between the capacitor-embeddedsubstrate 30 and external connection terminal 45, a detailed sectionalview thereof is shown in the lower part of FIG. 9. Specifically, aninsulating layer 46 having a via hole in a desired position on theelectrode 36 is formed on one surface of the second feedthroughelectrode 36 formed within the electrode (i.e., the first feedthroughelectrode) 33 of the capacitor in such a relationship that the electrode36 is insulated from the electrode 33 (by the insulating layer 35), andfurther, a wiring pattern (i.e., a Cu conductor) 47 of a desired shapeis formed on the insulating layer 46 including the via hole. The wiringpattern 47 is contained in the lowermost wiring layer of the multilayerwiring structure 41. Also, an insulating layer 48 having a via hole in adesired position on the second feedthrough electrode 36 is formed on theother surface of the electrode 36, and further, a wiring pattern (i.e.,a Cu pad portion) 49 in a desired shape is formed on the insulatinglayer 48 including the via hole, and a solder resist layer 50 is formedas an protective film with the pad portion 49 exposed. Further, theexternal connection terminal (i.e., the solder bump 45) is connected tothe pad portion 49 exposed from the solder resist layer 50.Incidentally, for bonding of the external connection terminal, it isdesirable that the pad portion 49 be plated with nickel (Ni) and gold(Au) in advance. This plating is for the purpose of improving adhesionto the pad portion for solder bonding and also improving electricalconductivity to the external connection terminal.

In the above-mentioned embodiments, description has been given takingthe case where a capacitor function alone is embedded in the silicon(Si) substrate; however, it is to be, of course, understood that apassive device embedded in the Si substrate is not limited to thecapacitor alone, taking into account the role of the capacitor-embeddedsubstrate (namely, the fact that the capacitor-embedded substrate isutilized as a base material or an interposer for a package or a modulemounting a semiconductor chip or the like thereon). For example, aninductor function may be embedded in the Si substrate.

Such an inductor function, although not specifically shown, can beformed in the same manner as the method shown in FIGS. 2A to 4D. Forexample, the formation of the inductor can be accomplished by forming anopening in a “spiral” pattern penetrating through the silicon (Si)substrate in the thickness direction thereof, and then filling aconductor such as copper (Cu) into the opening. In other words, theinductor function, in conjunction with any one of the capacitors of theabove-mentioned embodiments, may be collectively embedded in the same Sisubstrate. This contributes to a reduction in cost.

Also, the use of SiO₂ as an insulating layer on the Si substrate havingthe capacitor and inductor functions embedded therein enables theformation of finer multilayer wiring, thus enabling the utilization ofthe substrate as a compact and slim, high-density module wiring board.

Also, in the above-mentioned embodiments, description has been giventaking the case where the insulating layers 14, 24 and 34 made of SiO₂,obtained by thermally oxidizing or otherwise processing the surfaces ofthe silicon (Si) substrates 11, 21 and 31, respectively, are utilized asthe dielectric layers of the capacitors; however, it is to be, ofcourse, understood that a constituent material for the dielectric layeris not limited to this. It is essential only that the material be of thehighest possible permittivity, and for example, metal oxide such as BST(BaSrTiO₃: barium strontium titanate), BTO (BaTiO₃: barium titanate),STO (SrTiO₃: strontium titanate) or TiO_(x) (titanium oxide), resincontaining a filler of any one of these metal oxides, or the like may beused. MOCVD (metal organic chemical vapor deposition) method,sputtering, or the like can be used for deposition of these materials onthe base material.

Also, in the above-mentioned embodiments, description has been giventaking the case where the silicon (Si) substrate is used as the basematerial in which the passive device such as the capacitor is embedded;however, it is to be, of course, understood that an available basematerial is not limited to the Si substrate, as is apparent from thegist of the present invention (namely, a pair of conductors formed in adesired pattern shape penetrating through the base material in thethickness direction thereof are used as the electrodes of the capacitor,and the insulating layer interposed between the pair of electrodes isused as the dielectric layer of the capacitor, or equivalently, that thecapacitor is formed in three dimension within the base material). Forexample, a resin substrate generally used for a build-up wiring board, aceramic substrate or the like, may be used.

What is claimed is:
 1. A capacitor-embedded substrate comprising: a basematerial of silicon having a desired thickness; a pair of conductorsformed in respective desired patterns to penetrate completely throughthe base material in a thickness direction thereof, and oppositelydisposed with an insulating layer of silicon dioxide interposedtherebetween, wherein the pair of conductors is formed in respectivecomb-shaped patterns, and is oppositely disposed in such a manner thatrespective comb-tooth portions are meshed with each other, and the pairof conductors is divided into a plurality of divided portionselectrically insulated from each other, such that a plurality ofcapacitor portions are arranged; an upper insulating layer formed on theplurality of capacitor portions; via holes reaching the pair ofconductors in the plurality of capacitor portions, respectively; and awiring pattern formed on the upper insulating layer, and connecting theconductors of the plurality of capacitor portions through the via holes.